This invention relates to a driver circuit and, more particularly, to a driver circuit suited for driving a capacitive load.
For technical publications related to the present invention, see (1) the specification of Japanese Patent Kokai Publication JP-A-11-119750, and (2) the specification of Japanese Patent Kokai Publication JP-A-2000-338461.
FIG. 13 is a diagram illustrating one example of the structure of a driver circuit in a liquid crystal display device disclosed in the specification of Japanese Patent Kokai Publication JP-A-11-119750. As shown in FIG. 13, the driver circuit includes an N-channel MOS transistor 1011 whose source is connected to an input terminal T1 via a switch 1031 and whose gate and drain are tied together; a switch 1032 connected between the drain of the N-channel MOS transistor 1011 and a high-potential power supply VDD; an N-channel MOS transistor 1012 whose gate is connected in common with the gate of the N-channel MOS transistor 1011 (where the node at the point of connection is represented by V10) and whose drain is connected to the high-potential power supply VDD via a switch 1033; a P-channel MOS transistor 1021 whose source is connected to the input terminal T1 via a switch 1041 and whose gate and drain are tied together; a switch 1042 connected between the drain of the P-channel MOS transistor 1021 and the low-potential power supply VSS; and a P-channel MOS transistor 1022 whose gate is connected in common with the gate of the P-channel MOS transistor 1021 (where the node at the point of connection is represented by V20) and whose drain is connected to a low-potential power supply VSS via a switch 1043. The source of the N-channel MOS transistor 1012 and the source of the P-channel MOS transistor 1022 are connected in common and to an output terminal T2. The driver circuit further includes preliminary charging/discharging means constituted by a switch 1044 connected between the output terminal T2 and the high-potential power supply VDD and a switch 1034 connected between the output terminal T2 and the low-potential power supply VSS.
FIG. 14A is a timing chart illustrating the operation for controlling the switches in the conventional driver circuit of FIG. 13, and FIG. 14B is a diagram illustrating the voltage waveforms of the internal nodes V10, V20 and output voltage Vout of the conventional driver circuit of FIG. 13.
The operation for controlling the switches of the conventional driver circuit will be described with reference to FIG. 13 and FIGS. 14A, 14B.
First, at time t0, the switches 1032 and 1034 are turned on to establish a precharging mode, as a result of which the output voltage Vout declines. Since the switches 1031 and 1032 are off and on, respectively, under these conditions, the bias voltage at the gates of the transistors 1011 and 1012 is the power supply voltage VDD.
Next, at time t1, the switches 1031 and 1032 are turned on and off, respectively. As a result, owing to the action of the transistor 1011, the bias voltage changes to a voltage shifted from an input voltage Vin by an amount equivalent to a threshold value Vth1011 of the transistor 1011. Specifically, the bias voltage V10 is represented by the following equation:
V10=Vin+Vth1011
It should be noted that the threshold value Vth of the transistor is represented by a potential for which the source is the reference.
Next, at time t2, the switch 1034 is turned off, the precharging mode ends and the switch 1033 is turned on. Under these conditions, the transistor 1012 acts as a source follower and therefore the output voltage Vout changes to a voltage shifted from the bias voltage V10 at the gate of the transistor 1012 by an amount equivalent to a threshold value Vth1012 of the N-channel MOS transistor 1012. Specifically, the output voltage Vout is represented by the following equation:                     Vout        =                  V10          -          Vth1012                                        =                  Vin          +          Vth1011          -          Vth1012                    
If Vth1011≈Vth1012 holds, then Vout≈Vin will hold and the output voltage Vout will become approximately equal to the input voltage Vin.
At time t0xe2x80x2 (=t3), the switches 1042 and 1044 are turned on to establish the precharging mode, as a result of which the output voltage Vout rises. Since the switches 1041 and 1042 are off and on, respectively, under these conditions, the bias voltage at the gates of the transistors 1021, 1022 is the power supply voltage VSS.
Next, at time t1xe2x80x2, the switches 1041 and 1042 are turned on and off, respectively. As a result, owing to the action of the transistor 1021, the bias voltage changes to a voltage shifted from the input voltage Vin by an amount equivalent to a threshold value Vth1021 of the transistor 1021. Specifically, the bias voltage V20 is represented by the following equation:
V20=Vin+Vth1021
Next, at time t2xe2x80x2, the switches 1044 and 1043 are turned off and on, respectively, and the precharging mode ends. Under these conditions, the transistor 1022 acts as a source follower and therefore the output voltage Vout changes to a voltage shifted from the bias voltage V20 at the gate of the transistor 1022 by an amount equivalent to a threshold value Vth1022 of the transistor 1022. Specifically, the output voltage Vout is represented by the following equation:                     Vout        =                  V20          -          Vth1022                                        =                  Vin          +          Vth1021          -          Vth1022                    
If Vth1021≈Vth1022 holds with regard to the threshold voltages of the P-channel MOS transistors 1021 and 1022, then Vout≈Vin will hold and the output voltage Vout will become approximately equal to the input voltage Vin. It should be noted that in the case of an actual process for manufacturing a LSI chip, there are instances where the threshold voltage of a MOS transistor exhibits some variation. However, by forming the transistors 1011, 1012, 1021, 1022 close to one another and in the same size in the integrated circuit,
Vth1011≈Vth1012, Vth1021≈Vth1022
can be realized with comparative ease. Thus, the output voltage Vout can be made equal to the input voltage Vin and a data line DL can be driven with a high current supply capability owing to the source-follower action of the transistors.
This driver circuit is such that the transistors 1012 and 1022 function as source followers and little power is consumed because current other than that necessary for charging and discharging does not flow. However, it is difficult to drive the output voltage Vout to a voltage equal to the input voltage Vin rapidly. The reason for this is that in a transistor source-follower operation, most actual transistors have such a characteristic that the current driving capability varies gently while gradually decreasing when the gate-source voltage approaches the threshold voltage, as a result of which an extended period of time is required for the gate-source voltage to reach the vicinity of the threshold voltage and stabilize in the source-follower operation.
FIG. 15 is a diagram illustrating a driver circuit described in the specification of Japanese Patent Kokai Publication JP-A-2000-338461 (see FIG. 9 in the same specification). By controlling current in a source-follower driver circuit, it is possible to achieve rapid drive and produce a highly precise voltage output.
As shown in FIG. 15, this conventional driver circuit includes the N-channel MOS transistor 1011 whose source is connected to the input terminal T1 via the switch 1031 and whose gate and drain are tied together; a current source 1013 (current I11) connected between the drain of the N-channel MOS transistor 1011 and the high-potential power supply VDD; the N-channel MOS transistor 1012 whose gate is connected in common with the gate of the N-channel MOS transistor 1011 and whose drain is connected to the high-potential power supply VDD via the switch 1033; the switch 1032 connected between the common gates of the N-channel MOS transistors 1011 and 1012 and the high-potential power supply VDD; the P-channel MOS transistor 1021 whose source is connected to the input terminal T1 via the switch 1041 and whose gate and drain are tied together; a current source 1023 (current I21) connected between the drain of the P-channel MOS transistor 1021 and the low-potential power supply VSS; and the P-channel MOS transistor 1022 whose gate is connected in common with the gate of the P-channel MOS transistor 1021 and whose drain is connected to the low-potential power supply VSS via the switch 1043. The common gates of the P-channel MOS transistors 1021 and 1022 are connected to the low-potential power supply VSS via the switch 1042, the sources of the N-channel MOS transistor 1012 and P-channel MOS transistor 1022 are connected in common and to the output terminal T2. The driver circuit further includes preliminary charging/discharging means constituted by the switch 1044 connected between the output terminal T2 and the high-potential power supply VDD and the switch 1034 connected between the output terminal T2 and the low-potential power supply VSS. The driver circuit further includes a switch 1046 and a current source 1025 (current I23) between the output terminal T2 and the high-potential power supply VDD, a switch 1036 and a current source 1015 (current I13) between the output terminal T2 and the low-potential power supply VSS, a switch 1045 and a current source 1024 (current 122) between the input terminal T1 and the high-potential power supply VDD, and a switch 1035 and a current source 1014 (current I12) between the input terminal T1 and the low-potential power supply VSS. It is assumed that a capacitive load (not shown) has been connected to the output terminal T2.
The operation of the driver circuit shown in FIG. 15 will be described with reference to FIGS. 16A and 16B. FIG. 16A illustrates two output intervals, namely one output interval (times t0 to t3) in which a voltage of any level below voltage Vm is output, and a one output interval (times t0xe2x80x2 to t3xe2x80x2) in which a voltage of any level equal to or greater than voltage Vm is output. FIG. 16B is a voltage waveform diagram for a case where currents I11, I13, I21 and I23 are controlled so as to render equal the gate-source voltages Vgs1011(I11) and Vgs1012(I13) of the transistors 1011, 1012 as well as the gate-source voltages Vgs1021(I21) and Vgs1022(I23) of the transistors 1021 and 1022, thereby producing an output voltage Vout that is equal to the input voltage Vin. It should be noted that Vgs1011(I11) is a gate voltage (gate-source voltage) with respect to the source when the drain current of the transistor 1011 is I11.
At time t0 in FIG. 16, the switches 1032 and 1034 are turned on and all of the switches 1042, 1044, 1041, 1045, 1043 and 1046 are turned off. The node V10 is precharged to the voltage VDD via the switch 1032. At time t1, the switch 1032 is turned off and the switches 1031, 1035 are turned on, from which point the voltage V10 changes to a voltage shifted from the input voltage Vin by an amount equivalent to the gate-source voltage Vgs1011(I11) of the transistor 1011. The voltage V10 stabilizes at
V10=Vin+Vgs1011(I11) 
The output voltage Vout is discharged to the voltage VSS if the switch 1034 is turned on at time t0. If the switch 1034 is turned off and the switches 1033 and 1036 are turned on at time t2, then, from time t2 onward, the output voltage Vout changes to a voltage shifted from the input voltage Vin by an amount equivalent to the gate-source voltage Vgs1012(I13) of the transistor 1012 owing to the source-follower operation of the transistor 1012. The voltage Vout stabilizes at
Vout=V10xe2x88x92Vgs1012(I13) 
If Vgs1011(I11) and Vgs1012(I13) are positive values and the currents I11 and I13 are controlled so as to make these two voltages equal, then the output voltage Vout will become equal to the input voltage Vin. Further, the output-voltage range becomes
VSSxe2x89xa6Voutxe2x89xa6VDDxe2x88x92Vgs1012(I13) 
In the interval t0xe2x80x2 to t3xe2x80x2, the switches 1042 and 1044 are turned on and the switches 1032, 1034, 1031, 1035, 1033 and 1036 are all turned off at time t0xe2x80x2. The voltage V20 is discharged to the voltage VSS via the switch 1042. At time t1xe2x80x2, the switch 1042 is turned off and the switches 1041 and 1045 are turned on, from which point the voltage V20 changes to a voltage shifted from the input voltage Vin by an amount equivalent to the gate-source voltage Vgs1021(I21) ( less than 0) of the transistor 1021. The voltage V20 stabilizes at
V20=Vin+Vgs1021(I21) 
The output voltage Vout is precharged to the voltage VDD if the switch 1044 is turned on at time t0xe2x80x2. If the switch 1044 is turned off and the switches 1043 and 1046 are turned on at time t2xe2x80x2, then, from time t2xe2x80x2 onward, the output voltage Vout changes to a voltage shifted from the voltage V20 by an amount equivalent to the gate-source voltage Vgs1022(I23) ( less than 0) of the transistor 1022 owing to the source-follower operation of the transistor 1022. The voltage Vout stabilizes at                     Vout        =                  V20          -                      Vgs1022            ⁡                          (              I23              )                                                              =                  Vin          +                      Vgs1021            ⁡                          (              I21              )                                -                      Vgs1022            ⁡                          (              I23              )                                          
If Vgs1021(I21) and Vgs1022(I23) are negative values and the currents I21 and I23 are controlled so as to make these two voltages equal, then the output voltage Vout will become equal to the input voltage Vin. Further, the output-voltage range becomes
VSSxe2x88x92Vgs1022(I23)xe2x89xa6Voutxe2x89xa6VDD 
With the arrangement shown in FIG. 15, the switches 1031 and 1035 are ON from times t1 to t3, the switches 1033 and 1036 are on from times t2 to t3, the switches 1041 and 1045 are on from times t1xe2x80x2 to t3xe2x80x2 and the switches 1043 and 1046 are on from timings t2xe2x80x2 to t3xe2x80x2. As a result, an operation maintaining current is passed substantially steadily and static power consumption occurs. The Inventor has found that there is room for improvement in this regard.
FIG. 17 is a diagram illustrating a driver circuit described in the specification of Japanese Patent Kokai Publication JP-A-2000-338461 (see FIG. 12 in the same specification). The number of elements and the number of switching control signals are reduced over those of the arrangement shown in FIG. 15.
As shown in FIG. 17, this driver circuit is one in which the current control circuits 1014 and 1024 and the switches 1035 and 1045 have been eliminated from the arrangement of the driver circuit illustrated in FIG. 15 and to which a P-channel MOS transistor 1016 and an N-channel MOS transistor 1026 have been added anew. The P-channel MOS transistor 1016 has its source and drain connected to the gate (drain) and source, respectively, of the N-channel MOS transistor 1011, and has a voltage BIASP applied to its gate. The N-channel MOS transistor 1026 has its source and drain connected to the gate (drain) and source, respectively, of the P-channel MOS transistor 1021, and has a voltage BIASN applied to its gate. The voltage BIASP is supplied also to the gates of the P-channel MOS transistors 1013, 1025, and the voltage BIASN is supplied also to the gates of the N-channel MOS transistors 1015, 1023. The P-channel MOS transistor 1016 is made a transistor having a threshold voltage lower than that of the P-channel MOS transistor 1013 and a current supply capability sufficiently greater than that of the P-channel MOS transistor 1013 with respect to the same gate voltage. The N-channel MOS transistor 1026 also is made a transistor having a threshold voltage lower than that of the N-channel MOS transistor 1023 and a current supply capability sufficiently greater than that of the N-channel MOS transistor 1023 with respect to the same gate voltage. The circuit block consisting of the N-channel MOS transistor 1011 and P-channel MOS transistors 1013 and 1016 is represented by a circuit block 1010, and the circuit block consisting of the P-channel MOS transistor 1021 and N-channel MOS transistors 1023 and 1026 is represented by a circuit block 1020. The P-channel MOS transistor 1016 turns on when the input voltage Vin is in the vicinity of the power supply voltage VDD and the N-channel MOS transistor 1011 is about to turn off, and hence the transistor 1016 functions in such a manner that the current controlled by the current source 1013 flowing between the input terminal T1 and power supply VDD will not be cut off. Further, the N-channel MOS transistor 1026 turns on when the input voltage Vin is in the vicinity of the power supply voltage VSS and the N-channel MOS transistor 1021 is about to turn off, and hence the transistor 1026 functions in such a manner that the current controlled by the current source 1023 flowing between the input terminal T1 and power supply VSS will not be cut off. Accordingly, in the interval t0 to t3 in FIG. 16, the circuit block 1020 and switch 1041 can operate in a manner similar to that of the current source 1014 and switch 1035 in FIG. 15. In the interval t0xe2x80x2 to t3xe2x80x2 in FIG. 16, the circuit block 1010 and switch 1031 can operate in a manner similar to that of the current source 1024 and switch 1045 in FIG. 15. As a result, the circuit of FIG. 17 can perform drive in a manner similar to the voltage waveforms shown in FIG. 16A.
As with the driver circuit shown in FIG. 15, an operation maintaining current is passed substantially steadily and static power consumption occurs in the circuit illustrated in FIG. 17. The Inventor has found that there is room for improvement in this regard.
Accordingly, it is an object of the present invention to provide a driver circuit that performs a follower operation, in which it is possible to produce a highly precise output while reducing power consumption, as well as a liquid crystal display device having this driver circuit.
In accordance with a first aspect of the present invention, the foregoing object is attained by providing a driver circuit comprising a follower transistor arranged between an output terminal and a first power supply; a first control means for controlling activation and deactivation of the transistor; a current source arranged between the output terminal and a second power supply; a second control means for controlling activation and deactivation of the current source; and bias control means for supplying the transistor with an input bias voltage based upon an input signal voltage; wherein control is made such that said transistor is activated while said current source is deactivated at one timing in a data output interval, thereby causing said transistor to perform a follower operation, and then from a timing subsequent to the said one timing onward, both said transistor and said current source are activated to cause the output terminal voltage to be driven to a certain voltage, which is defined in conformity with the input signal voltage.
A driver circuit in accordance with another aspect of the present invention, comprises a follower transistor and a first switch connected serially between an output terminal and a first power supply; a first current source and a second switch connected serially between the output terminal and a second power supply; and bias control means for supplying the follower transistor with an input bias voltage based upon an input signal voltage; wherein the first switch is turned on at one timing in a data output interval, thereby causing the transistor to perform a follower operation to drive the output terminal voltage to the vicinity of a certain voltage defined in conformity with the input signal voltage; the second switch is turned on at a timing subsequent to the one timing, thereby placing both the first and second switches in the ON state; and the output terminal voltage is driven to the certain voltage, which is defined in conformity with the input signal voltage, from the subsequent timing onward.
In accordance with a further aspect of the present invention, the foregoing object is attained by providing a driver circuit comprising a source-follower first MOS transistor of first conductivity type and a first switch connected serially between an output terminal and a high-potential power supply; a first current source and a second switch connected serially between the output terminal and a low-potential power supply; first gate bias control means for supplying the first MOS transistor with a gate bias voltage based upon an input signal voltage; and means for turning on the first switch at one timing in a data output interval, thereby causing the first MOS transistor to perform a source-follower operation to drive the output terminal voltage to the vicinity of a certain voltage defined in conformity with the input signal voltage, and turning on the second switch at a timing subsequent to the one timing, thereby placing both the first and second switches in the ON state; wherein the output terminal voltage is driven to the certain voltage, which is defined in conformity with the input signal voltage, from the subsequent timing onward, which is for controlling drain current of the first MOS transistor.
Further, a driver circuit according to the present invention comprises a source-follower second MOS transistor of second conductivity type and a third switch connected serially between an output terminal and a low-potential power supply; a second current source and a fourth switch connected serially between the output terminal and a high-potential power supply; second gate bias control means for supplying the second MOS transistor with a gate bias voltage based upon an input signal voltage; and means for turning on the third switch at one timing in a data output interval, thereby causing the second MOS transistor to perform a source-follower operation to drive the output terminal voltage to the vicinity of a certain voltage defined in conformity with the input signal voltage, and turning on the fourth switch at a timing subsequent to the one timing, thereby placing both the third and fourth switches in the ON state; wherein the output terminal voltage is driven to the certain voltage, which is defined in conformity with the input signal voltage, from the subsequent timing onward, which is for controlling drain current of the second MOS transistor.
In the present invention, the first gate bias control means includes a third MOS transistor of first conductivity type having a drain and gate connected in common with a gate of the first MOS transistor and a source connected to the input terminal via a fifth switch; a third current source and a sixth switch connected serially between the drain of the third MOS transistor and the high-potential power supply; a fourth current source and a seventh switch connected serially between a connection node of the input terminal and fifth switch and the low-potential power supply; and an eighth switch connected between a common connection node of the gates of the first and third MOS transistors and the high-potential power supply.
In the present invention, the second gate bias control means includes a fourth MOS transistor of second conductivity type having a drain and gate connected in common with a gate of the second MOS transistor and a source connected to the input terminal via a ninth switch; a fifth current source and a tenth switch connected serially between the drain of the fourth MOS transistor and the low-potential power supply; a sixth current source and an 11th switch connected serially between a connection node of the input terminal and ninth switch and the high-potential power supply; and a 12th switch connected between a common connection node of the gates of the second and fourth MOS transistors and the low-potential power supply.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings wherein only the preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.